1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a memory device, such as a dynamic random access memory (DRAM) provided with memory cell transistors (or access transistors).
2. Description of the Related Art
In recent years, the application of DRAMs has spread to portable appliances and, therefore, the information retention characteristic thereof has become more important than ever. The current consumption and the power consumption of a DRAM are closely related to the information retention characteristic thereof. In general, the more excellent the information retention characteristic is, the smaller the current consumption and the power consumption can be made. The DRAM stores information by means of charge accumulation into capacitive elements. However, the accumulated charges dissipate along with the lapse of time. The information retention characteristic of the DRAM is dominated primarily by this charge dissipation characteristic.
In order to explain the mechanism of this charge dissipation, an explanation will be made of a method of manufacturing memory cell transistors as a first related art. Note that the explanation assumes that the memory cell transistors are N-type MOS transistors.
First, pad oxide film 102 and pad nitride film 103 are sequentially deposited on silicon substrate 101. Next, the pad nitride film, the pad oxide film and the silicon substrate having a predetermined depth (thickness) in portions where element-isolating regions are to be formed are selectively removed using photolithography and dry etching techniques to form trench 104 (FIG. 1a). Next, an insulating film is formed so as to fill the trench. Then, chemical-mechanical polishing (CMP) is performed using pad nitride film 103 as a polish stop layer to form element-isolating region 105 (FIG. 1b).
Next, after sequentially removing the pad nitride film and the pad oxide film using a hot phosphoric acid solution and a fluorinated acid solution, respectively, oxide film (buffer oxide film) 106 is formed anew on the exposed silicon substrate (FIG. 1c). Then, a P well (not shown in the figure) is formed using an ion implantation technique by introducing a P-type impurity to a position relatively distant from the silicon surface. In addition, channel impurity region 107 is formed by introducing a p-type impurity to the vicinity of the silicon substrate surface across the entire memory cell transistor area for the purpose of controlling the threshold voltage of a memory cell transistor (FIG. 1d).
Next, after removing the buffer oxide film using a fluorinated acid solution, gate oxide film 111, conductive film for gate electrodes 112, and insulating film for gate electrode processing 113 are sequentially deposited (FIG. 1e).
Next, the conductive film for gate electrodes is processed to predetermined dimensions using photolithography and dry etching techniques to form gate electrodes. Next, an N-type impurity is introduced using an ion implantation technique to form source/drain regions 114a and 114b of the memory cell transistor (FIG. 1f).
Next, after forming sidewall insulating films 115 on the side surfaces of the gate electrodes in a usual way, the entire memory cell area is buried with interlayer insulating film 116. Next, contact holes are formed for the source/drain regions. Then, a conductive material is filled in the contact holes to form extraction electrodes 117 (FIG. 1g).
In FIG. 1g, a storage capacitor is to be connected to the leftmost and rightmost electrodes among the three extraction electrodes and a bit line is to be connected to the middle extraction electrode. In the following description, a region where each storage capacitor-side extraction electrode and the silicon substrate are in contact with each other is referred to as a storage capacitor contact, and a region where the bit line-side extraction electrode and the silicon substrate are in contact with each other is referred to as a bit line contact, as appropriate. In addition, source/drain region 114a on the storage capacitor side is referred to as a storage capacitor-side diffused layer, and source/drain region 114b on the bit line side is referred to as a bit line-side diffused layer. Furthermore, an impurity introduced to the vicinity of the silicon substrate surface for the purpose of threshold voltage control is referred to as a channel impurity.
As the mechanisms of charge dissipation in a memory cell transistor formed as described above, there are a sub-threshold leakage current and a junction leakage current.
The sub-threshold leakage current is a current that flows from the drain to the source of the memory cell transistor in a state wherein the gate potential of the memory cell transistor is off. The magnitude of this current depends on the threshold voltage of the memory cell transistor. In order to control the sub-threshold leakage current to within given tolerance limits, the threshold voltage of the memory cell transistor must be maintained to be no smaller than a specific value. To this end, the concentration of the channel impurity must be set to a high level.
The junction leakage current is a current that flows from the storage capacitor-side diffused layer to the silicon substrate. The magnitude of this current depends on the electric field strength of a PN junction between the storage capacitor-side diffused layer and the silicon substrate. In order to suppress the junction leakage current, it is necessary to relax the junction electric field. In order to relax the junction electric field, it is conceivable to lower the impurity concentration of either the storage capacitor-side diffused layer or the silicon substrate. In the latter case, the impurity concentration of the silicon substrate is fixed by the channel impurity concentration. Hence in practice, the junction electric field is relaxed by setting the channel impurity concentration to a low level.
However, it is difficult to simultaneously suppress both the sub-threshold leakage current and the junction leakage current by adjusting the channel impurity concentration. Now assuming, for example, that the channel impurity concentration is lowered in an attempt to suppress the junction leakage current, then the threshold voltage of the memory cell transistor drops. As a result, the sub-threshold leakage current increases. Conversely, if the channel impurity concentration is heightened in an attempt to suppress the sub-threshold leakage current, then the junction leakage current increases. In this way, there exists a trade-off relationship in principle between the suppression of the sub-threshold leakage current and the suppression of the junction leakage current.
This trade-off relationship is particularly noticeable in increasingly miniaturized elements. In general, the threshold voltage of a MOS transistor drops as element dimensions diminish. This phenomenon is referred to as a short channel effect. Hence, the channel impurity concentration is set to a higher level than ever when reducing the element dimensions, in order to compensate for the threshold voltage drop due to the short channel effect. As a result, the junction leakage current increases. In this way, it has become increasingly difficult, along with the advance of miniaturization, to simultaneously suppress both the sub-threshold leakage current and the junction leakage current.
Next, a description will be made of the impurity concentration of the storage capacitor-side diffused layer. As described above, it is preferable from the viewpoint of electric field relaxation that the impurity concentration of the storage capacitor-side diffused layer be low. However, if the impurity concentration of the storage capacitor-side diffused layer is lowered excessively, the following two problems arise. First, the current driving capability of a transistor degrades as the result of an increase in the resistance of the source/drain region. Second, deterioration resistance against hot carriers degrades. The mechanism of deterioration is that the depletion of the drain region occurs and the resistance thereof increases due to hot carriers trapped, for example, in an interface between the gate-insulating film and the silicon substrate and turned into fixed charges. Note here that the lower is the impurity concentration of the diffused layer, the higher is the degree of the depletion. That is, the deterioration resistance degrades if the impurity concentration of the diffused layer is lowered. For this reason, there is a lower limit that can be set for the impurity concentration of the storage capacitor-side diffused layer. This lower limit can be set to a smaller value for lower channel impurity concentrations. This is because the above-described problems are less likely to occur if the channel impurity concentration is low.
Incidentally, the channel impurity need not be distributed across the entire memory cell transistor area. It is only necessary for the channel impurity to be distributed in regions immediately below the gate electrodes (channel regions). A variety of techniques that take advantage of this fact are under consideration. One of these techniques is described in the Related Art section of Japanese Patent Laid-Open No. 2004-274031 (Patent Document 1). Hereinafter, an explanation will be made by defining this technique as a second related art.
In the above-described first related art, the channel impurity is introduced across the entire memory cell transistor area. In contrast, in the second related art, the region of channel impurity distribution is restricted using a mask for forming openings in the regions which correspond to the regions where a region for a gate electrode to be formed later and a region for a bit line contact to be formed later are overlapped with each other. Hereinafter, the mask used for the purpose of restricting the region of channel impurity distribution is referred to as the “channel impurity mask.”
FIG. 2a shows an example of disposing active region (non-element-isolating region) 201, opening position for channel impurity mask 202 and gate electrode 112.
FIG. 2b is a cross-sectional view illustrating a step of channel impurity introduction. The step shown in FIG. 2b corresponds to the above-described step shown in FIG. 1d. After forming element-isolating region 105, buffer oxide film 106 and a well (not shown in the figure) on silicon substrate 101 in the same as the first related art, resist mask 203 having an opening only in a predetermined region is formed using a photolithography technique making use of the channel impurity mask. Subsequently, a channel impurity is introduced to the vicinity of the silicon substrate surface using an ion implantation technique to form channel impurity region 107. After that, a memory cell transistor is completed by going through the same steps as those of the first related art (FIG. 2c).
Storage capacitor-side diffused layer 114a of the memory cell transistor formed as described above is not in contact with channel impurity region 107, as shown in FIG. 2c. Since this has virtually the same effect as a decrease in the channel impurity concentration, a storage capacitor-side junction electric field is relaxed and, therefore, the junction leakage current decreases. Concurrently, a predetermined threshold voltage can be obtained since there are sufficient amounts of channel impurity in silicon regions below the gate electrodes (channel regions). In this way, there is obtained the effect of simultaneously suppressing both the sub-threshold leakage current and the junction leakage current. Note that although the junction electric field of bit line-side diffused layer 114b is not relaxed, this does not affect the information retention characteristic.
However, the second related art has the problems noted below.
As has been already described, it is preferable from the viewpoint of junction leakage current that the source/drain impurity concentration be low. In the second related art, however, a larger amount of the source/drain impurity than necessary is implanted into the storage capacitor-side diffused layer. Consequently, the effect of electric field relaxation provided by restricting the region of channel impurity distribution is reduced. As a result, the effect of suppressing the junction leakage current reduces. This is the first problem with the second related art. A further explanation will be made of this problem. The amount of implanted source/drain impurity ions is fixed due to requirements for the formation of the PN junction of the bit line-side diffused layer. That is, since the channel impurity is distributed in the bit line-side contact region, the source/drain impurity must be implanted at a concentration higher than the channel impurity concentration, in order to form the PN junction of the diffused layer there. On the other hand, since the channel impurity is not distributed in the storage capacitor-side contact region, the amount of ions originally required to be implanted to form the storage capacitor-side PN junction may be smaller than the amount required for the bit line-side contact region. However, since PN junctions must be formed on the bit line side and on the storage capacitor side by a single step of source/drain impurity introduction, a larger amount of the source/drain impurity than necessary is implanted into the storage capacitor-side diffused layer.
The second problem in the second related art is that the related art is susceptible to the effect of mask misalignment in a manufacturing process. FIG. 3a shows a cross-sectional view of a step of channel impurity introduction when a channel impurity mask is misaligned to the right with respect to positions wherein a diffused layer and a gate are to be formed. FIG. 3b shows a cross-sectional view in a condition after a memory cell transistor is formed. In this case, there arises the problem in one transistor on the right side of the figure that the storage capacitor-side junction electric field increases. This is because channel impurity region 107 and storage capacitor-side diffused layer 114a come into direct contact with each other. Likewise, there arises the problem in the other transistor on the left that the threshold voltage drops. This is because the total amount of the channel impurity distributed in the silicon regions below the gate electrodes falls short of a predetermined value.
Note that Patent Document 1 proposes letting an element-isolating film protrude from the substrate surface and performing self-aligned inclined ion implantation using this protruding element-isolating film as a mask, in order to solve problems resulting from mask misalignment. With this method, however, it is not possible to obtain a sufficient effect of decreasing junction electric fields since a channel impurity is also implanted into regions other than those immediately below gate electrodes.
As a solution to the second problem in the second related art, Japanese Patent Laid-Open No. 10-56147 (Patent Document 2) describes a technique to let a channel impurity distribute in a self-aligned manner with respect to gate electrodes. Hereinafter, an explanation will be made with this technique defined as the third related art.
In the third related art described in Patent Document 2, the introduction of a channel impurity is carried out by means of self-aligned inclined ion implantation making use of a gate pattern portion as a mask.
FIG. 4a shows an example of disposing active region (non-element-isolating region) 201, mask opening position 202 and gate electrode 112.
FIG. 4b is a cross-sectional view illustrating a step of channel impurity introduction. After forming gate electrodes, there is formed mask 203 (channel impurity mask) for opening up a region for a bit line-side diffused layer. Using this mask and exposed gate pattern portions 112 and 113 also as masks, a channel impurity is introduced by performing ion implantation from an oblique direction to form channel impurity region 107. After that, a memory cell transistor is completed by going through the same steps as those of the first related art (FIG. 4c).
In the third related art, there is obtained an effect of simultaneously suppressing both the sub-threshold leakage current and the junction leakage current. The reason for this is the same as in the second related art. In addition, in the third related art, it is possible to precisely form the channel impurity region without being affected by mask misalignment since exposed gate pattern portions 112 and 113 are used as masks. This is because the position of the channel impurity based on the gate electrodes is determined in a self-aligned manner.
However, the third related art has the three problems described below.
The first problem is that like the first problem with the second related art, it is not possible to obtain a sufficient effect of decreasing the junction leakage current since a larger amount of the source/drain impurity than necessary is implanted into the storage capacitor-side diffused layer.
The second problem is that in a photolithography step for forming a channel impurity mask, it is difficult to obtain a sufficient focal depth margin and a sufficient light intensity margin. Under normal conditions, a lithography step concerned with memory cell processing is carried out after planarization processing has been performed previously. This is for the purpose of obtaining a focal depth margin or a light intensity margin necessary for manufacturing. In the third related art, however, high-precision photolithography must be carried out under the condition in which there are undulations (differences of elevation or steps) caused by the gate pattern portions. As a result, it is difficult to obtain a sufficient focal depth margin and a sufficient light intensity margin.
The third problem is a constraint on the angle of ion implantation. Angle-of-inclination range R that can be set in ion-implanting the channel impurity is determined by interval between adjacent gates S and height of gate pattern portions H (FIG. 4d). Note here that interval between adjacent gates S decreases along with an advance in miniaturization. In addition, the gate electrode becomes higher also along with an advance in miniaturization. This is because an increase in resistance due to a reduction in element dimensions is compensated by the height (thickness) of gate electrodes. Consequently, the angle-of-inclination range that can be set when implanting the channel impurity becomes narrower along with an advance in miniaturization. This means that in an increasingly miniaturized element, it is difficult to implant a sufficient amount of the channel impurity into a channel region in order to obtain a predetermined threshold voltage.
As described above, in the first related art, it is in principle difficult to simultaneously suppress both the sub-threshold leakage current and the junction leakage current.
In the second related art, although an effect of simultaneously suppressing the sub-threshold leakage current and the junction leakage current is obtainable, the impurity concentration of the storage capacitor-side source/drain region becomes higher than necessary. Thus, the second related art has the problem that it is not possible to obtain a sufficient effect of suppressing the junction leakage current. In addition, the second related art is liable to the problem of mask misalignment in a step of forming the channel impurity region. As a result, it is difficult to control the threshold voltage of the memory cell transistor, thereby causing the sub-threshold leakage current to increase, or the storage capacitor-side diffused layer and the channel impurity region to come into direct contact with each other, resulting in an increase in the junction leakage current.
In the third related art, although an effect of simultaneously suppressing the sub-threshold leakage current and the junction leakage current is obtainable, the impurity concentration of the storage capacitor-side source/drain region becomes higher than necessary. Thus, the third related art has the same problem as the second related art that it is not possible to obtain a sufficient effect of suppressing the junction leakage current. In addition, in the third related art, although there is obtained an effect of suppressing mask misalignment in a step of forming the channel impurity region, there is the problem that a photolithography step for the purpose of forming the mask becomes difficult to perform. Furthermore, the degree of constraint on the angle of implantation at the time of channel impurity implantation becomes higher along with an advance in miniaturization. Thus, there is the problem that it is not possible to form a desired channel impurity region.